In order to enhance performance, central processing unit (CPU) products are increasingly integrating multiple die within the CPU package in a side-by-side or other multi-chip-package (MCP) format. This development, along with other factors such as the long-standing trend toward increasing the density of transistors, requires high density die to die connections (measured by input/output (I/O) per millimeter (mm) of die edge per layer) for overall CPU performance improvement. Die to die connections are usually built through organic substrates with relative coarse circuit routing, which makes it difficult to increase the density of die to die connection to match the miniaturization trend within the die.
To overcome bandwidth limitations between logic-logic and/or logic-memory communications in MCPs, embedded silicon bridges (SiB) have been proposed as a means to achieve high density die-to-die interconnection. One approach for connecting through the package to the embedded bridge die may involve using ultra-small interconnection paths (via) having smallest possible interconnection pitches (spacing between adjacent via). However, it may be extremely difficult to scale a via pitch in organic package substrate to a desired size with current technology.